1. Field of the Invention
The invention generally relates to the field of semiconductor integrated circuit design and, more particularly, to non-planar static random access memory (SRAM) cell design.
2. Description of the Related Art
Integrated circuit design decisions are often driven by device scalability and manufacturing efficiency. For example, size reduction of single-gate planar metal oxide semiconductor field effect transistors (MOSFETs) often results in reduced drive current because the width of the device is associated with the drive. In response, multi-gated non-planar transistors, such as double-gated FETs (e.g., fin-type FETs (finFETs)) or trigate FETs, were developed to provide scaled devices with faster drive currents and reduced short channel effects.
FinFETs are non-planar transistors in which a fully depleted channel region is formed in the center of a thin semiconductor fin with source and drain regions in the opposing ends of the fin adjacent to the channel region. Gates are formed each side of the thin fin in an area corresponding to the channel region. The effective fin width is determined by the fin height (e.g., short wide fins can cause partial depletion of a channel). For a double-gated fin-FET, a fin thickness of approximately one-fourth the length of the gate (or less) can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. Additionally, the effective channel width of a finFET device can be increased by using multiple fins.
Trigate MOSFETs have a similar structure to that of finFETs; however, the fin width and height are approximately the same so that gates can be formed on three sides of the channel, including the top surface and the opposing sidewalls. The height to width ratio is generally in the range of 3:2 to 2:3 so that the channel will generally remain fully depleted and the three-dimensional field effects of a trigate MOSFET will give greater drive current and improved short-channel characteristics over a planar transistor. As with finFETs, the effective channel width of a trigate MOSFET can be increased by using multiple fins. For a detail discussion of the structural differences between dual-gate finFETs and tri-gate MOSFETs see “Dual-gate (finFET) and Tri-Gate MOSFETs: Simulation and Design” by A Breed and K. P. Roenker, Semiconductor Device Research Symposium, 2003, pages 150-151, December 2003 (incorporated herein by reference).
Recently, static random access memory (SRAM) cells (e.g., 6T-SRAM cells having two pass-gate transistors, two pull-up transistors and two pull-down transistors) have incorporated such non-planar multi-gate FETs. Such SRAM cells can be formed, for example, using silicon-on-insulator (SOI) wafers, bulk wafers or hybrid orientation wafers. However, due to the conventional lithographic techniques used to pattern the fins (regardless of the type of wafer used), it is difficult to fit the multiple fins required to achieve an effective width and, thereby, sufficient drive current for non-planar multi-gate SRAM cells, and particularly, for the pull-down FETs of SRAM cells, in the same space as a planar SRAM cell. Additionally, frequency doubling of fin pitch is not easily achieved using current state of the art lithographic technology, and thus, trigate or finFET SRAM cells may be compromised for either density or performance. Therefore, there is a need for a dense high-speed non-planar multi-gate SRAM cell in which drive current of the pull-down FETs can be maintained or increased without a corresponding increase in deleterious short-channel effects despite a reduction in cell size.